1. Field of the Invention
The present invention relates to a Silicon On Insulating (SOI) substrate and its method of manufacture, and in particular, relates to an SOI substrate that is useful in a power IC, and its method of manufacture.
2. Description of the Related Art
When monolithically integrating high-voltage vertical power elements and control circuit elements having current routes from the front to rear surface of a silicon substrate, partial SOI substrates are used that have been treated so as to allow the formation of only the control circuit elements on the SOI layer. This type of partial SOI substrate is disclosed in Japanese patents laid-open No. 29353/92 and No. 82138/91.
FIG. 1 shows sectional views of the progression of steps in a manufacturing method of SOI substrates (to be referred to as "the first example of the prior art") disclosed in Japanese patent laid-open No. 29353/92.
First, as shown in FIG. 1a, a photoresist is formed by photolithography in a prescribed pattern on one main surface of an n.sup.+ -type silicon single crystal substrate 4. This photoresist is used as a mask to form a shallow step by, for example, an ion etching method, and an SiO.sub.2 insulation film 2 is formed by a method such as thermal oxidation or low-temperature chemical vapor deposition (CVD).
Next, as shown in FIG. 1b, the protruding step portion of the insulation film 2 is removed by means of grinding-polishing or etching, and the exposed surface of the n.sup.+ -type silicon single crystal substrate 4 and the insulation film 2 are leveled.
The level surface obtained by the above-described steps is bonded to one main surface of an n.sup.- -type silicon single crystal substrate 1 and subjected to heat treatment to obtain a single firmly bonded compound substrate (FIG. 1c). Next, the n.sup.- -type silicon single crystal substrate 1 is ground and polished as far as the Y--Y plane shown in FIG. 1c to make the silicon substrate 1 a desired thickness as well as to level its surface. Next, an insulation film is formed on this leveled surface, the insulation film is patterned by means of photoetching, and using this film as a mask, alkali etching is carried out to form isolation grooves for isolation, thereby both isolating a vertical power element formation zone 6 and a control circuit element formation zone 7 and dividing the silicon single crystal substrate 1 of control circuit element formation zones 7 into silicon single crystal islands 8.
Next, an insulation film 9 composed of, for example SiO.sub.2, is formed across the entire surface of the n.sup.- -type silicon single crystal substrate 1 by thermal oxidation or low-temperature CVD, following which a polycrystalline silicon layer 10 is formed by CVD. The polycrystalline silicon layer 10 and insulation film 9 on the substrate main surface are next removed by grinding-polishing or etching, leaving the isolation grooves covered by the insulation film 9 and polycrystalline silicon film 10 to produce an SOI substrate with insulated and isolated element formation zones (FIG. 1d).
Next, as another example of the prior art to be referred to hereinbelow as "the second prior art example," explanation is given with reference to FIG. 2 regarding the partial SOI substrate disclosed by Japanese patent laid-open No. 82138/91.
First, as shown in FIG. 2a, a prescribed portion of one main surface of an n.sup.- -type silicon single crystal substrate 1 is oxidized by a selective oxidation method to form a LOCOS oxide film 11. Next, as shown in FIG. 2b, on the side of the silicon substrate 1 on which the LOCOS oxide film has formed, epitaxial growth of silicon is carried out by CVD to form an n.sup.+ -type silicon single crystal layer 14 on the portion of the main surface of the n.sup.- -type silicon single crystal substrate 1 not covered by the LOCOS oxide film 11, and a polycrystalline silicon layer 3 is formed on the LOCOS oxide film 11. Next, a mechanochemical grinding method is employed to grind as far as the X--X plane to make the surfaces of the n.sup.+ -type silicon single crystal layer 14 and the polycrystalline silicon layer 3 a single level plane.
Next, as shown in FIG. 2c, an n.sup.+ -type silicon single crystal substrate 4 is bonded to the flat plane of the n.sup.+ -type silicon single crystal layer 14 and the polycrystalline silicon layer 3 formed on the main surface of the n.sup.- -type silicon single crystal substrate 1, and a heat process is carried out to obtain a single compound substrate.
Finally, as shown in FIG. 2d, the surface of the n.sup.- -type silicon single crystal substrate 1 is ground and polished as far as the Y--Y plane shown in FIG. 2c to produce a level surface, following which, by diffusing p-type impurities at high concentration at prescribed locations to form p.sup.+ -type diffusion layers 12, a vertical power element formation zone 6 and a control circuit element formation zone 7 are isolated and the silicon single crystal substrate 1 of the control circuit element formation zone 7 is divided into silicon single crystal islands 8.
In the first example of the prior art described hereinabove, silicon single crystal and silicon oxide film (or silicon nitride film) are mixed on the bonding surface of an SOI substrate, and in the second example of the prior art, silicon single crystal and polycrystalline silicon are mixed on the bonding side of an SOI substrate. When leveling a surface in which differing substances are mixed in this way, suppressing variations in surface level to less than 100 .ANG. is extremely difficult using current grinding or etching technology. For this reason, insufficient flatness in the bonding surface may give rise to voids in the bonded plane, and as a consequence, there is the problem that peeling may originate from the vicinity of these voids during subsequent heat treatments, thereby causing the vertical power elements to be inoperable.